if the memory is constructed as fou

if the memory is constructed as four interleaved modules, then when the starting address of the block arrives at the memory, all four modules being accessing the required data using the high-order bits of the address. After 8 clock cycles, each module has one word of data in its DBR. These words are transferred to the cache one word at a time during the next 4 clock cycles. During this time, the next word in each module is accessed. Then it takes another 4 clock cycles to transfer these words to the cache.

if the memory is constructed as four interleaved modules, then when the starting address of the block arrives at the memory, all four modules being accessing the required data using the high-order bits of the address. After 8 clock cycles, each module has one word of data in its DBR. These words are transferred to the cache one word at a time during the next 4 clock cycles. During this time, the next word in each module is accessed. Then it takes another 4 clock cycles to transfer these words to the cache.

If the memory is constructed as four interleaved modules then when, the starting address of the block arrives at, the memory. All four modules being accessing the required data using the high-order bits of the address. After 8, clock cycles each. Module has one word of data in its DBR. These words are transferred to the cache one word at a time during the next 4 clock. Cycles During, this time.The next word in each module is accessed. Then it takes another 4 clock cycles to transfer these words to the cache.
.